1. Field of the Invention
The present invention relates to a transposing memory, and more particularly, to a device that generates memory addresses.
2. Background of the Related Art
A transposing memory is used in an encoder, decoder, or an interleaver in a mobile communication system. For a mobile station having a picture transmission function, the encoder encodes a picture data for transmission of the picture to an opposite party, and the decoder receives and decodes the encoded picture data into an original picture data. The interleaver is provided for minimizing a burst error of the data transmitted in a CDMA type communication system.
The encoder and decoder of the mobile station will now be described. FIG. 1 illustrates a block diagram showing a part of a related art encoder.
As shown in FIG. 1, the related art encoder is provided with a 2D DCT part 100 for receiving, and twice subjecting a picture data to Discrete Cosine Transform (DCT), a quantizing part 110 for receiving and quantizing the picture data from the DCT part 100, and a zigzag scanning block 120 for scanning DC and AC components of the picture data quantized at the quantizing part 110 in a zigzag for encoding the DC and the AC components. A Variable Length Coding (VLC) part 130 is for assigning codes of short lengths to symbols with a high frequency of occurrences in view of probability, and assigning codes of long lengths to symbols with a low frequency of occurrences. A channel buffer 140 buffers the encoded picture data. An inverse quantizing part 150 is for subjecting the DCT data from the quantizing part 110 to inverse quantizing, and a 2D IDCT part 160 is for twice subjecting the DCT data from the inverse quantizing part 150 to Inverse Discrete Cosine Transform (IDCT).
The 2D DCT part 100 is provided with a first DCT 101 for receiving and subjecting the picture data to DCT, a transposing memory 102 for storing the DCT picture data in a row direction and presenting in a column direction and a second DCT 103 for subjecting the data from the transposing memory 102 to DCT. A row direction address generator 104 generates a writing address of the transposing memory 102, and a column direction address generator 105 generates a reading address of the transposing memory 102.
The 2D IDCT part 160 is provided with a first IDCT 163 for receiving and subjecting the DCT data from the inverse quantizing part 150 to IDCT, a transposing memory 162 for temporary storing the IDCT data in the row direction and presenting in a column direction and a second IDCT 161 for subjecting the data from the transposing memory 162 to IDCT. A row direction address generator 164 generates a writing address of the transposing memory 162, and a column direction address generator 165 generates a reading address of the transposing memory 162. The zigzag scanning block 120 is provided with a zigzag scanning part 121 for zigzag scanning the quantized data. A column direction address generator 122 and a zigzag address generator 123 provide a scanning and an output address to the zigzag scanning part 121, respectively. A detailed description of the decoder will be omitted here as the decoder has a system opposite to the encoder.
The operation of the related art encoder will now be described. The picture data has a high correlation between adjacent data. Therefore, a two dimensional data operation, such as DCT, is processed by twice performing a one dimensional operation using orthogonal transform characteristics. Thus, the data subjected to a first one dimensional operation at the first DCT 101 is stored in the transposing memory 102 according to the writing address generated in the row direction at the row direction address generator 104. The data stored in the row direction in the transposing memory 102 is presented by the reading address generated in the column direction at the column direction address generator 105 and subjected to a one dimensional operation for the second time at the second DCT 103. The foregoing process is applicable to the IDCT process, except that the data is stored according to a writing address generated in the row direction at the transposing memory 162 in the 2D IDCT part 160, and presented in the column direction according to a reading address generated in the column direction. In the meantime, the data is provided to the zigzag scanning part 121 according to the column direction writing address provided from the column direction address generator 122. States of the picture data input to/output from the transposing memory 102 are shown in FIGS. 2A and 2B, respectively.
The column direction address generator in the related art encoder will now be described. FIG. 3 illustrates row/column direction address generators shown in FIG. 1.
As shown in FIG. 3, since the data from the transposing memory 102 or 162 has a transposed matrix, the column direction address generator is required to provide the reading address for presenting the data stored in the transposing memory 102 and 162. Therefore, the column direction address generator 105 or 164 is provided with a first counter 300 for providing an 2n (i.e., 0, 1, 2, 3, 4, 5, 6, 7 when n=3) by up counting a pulse signal every time the pulse signal is provided to an enable terminal. An initial value generator 310 takes a new value from the first counter 300 as an initial value every time the new value is provided from the first counter 300. A second counter 330 is for repeatedly counting 2n to generate a carry out signal whenever the count is 2n, and provide the carry out signal to the first counter 300 and the initial value generator 310 as an enable signal. Further, a step sizer 340 always provides 2n, and an accumulator 320 accumulates the 2n value from the step sizer 340 for 2n times using the signal from the initial value generator 310 as an initial value and then forwards the accumulated value.
The operation of the column direction address generator will now be described. As shown in FIG. 4, it is assumed that the transposing memory 102 or 162 is a square of 2nxc3x972n. Thus, when the first counter 300, the second counter 330, and the initial value generator 310 are initialized, the first counter 300 provides xe2x80x980xe2x80x99 so that the initial value generator 310 initializes the accumulator 320 at xe2x80x980xe2x80x99 for the accumulator 320 to provide an address of xe2x80x980xe2x80x99. Next, the accumulator 320 adds the 2n from the step sizer 340 to provide 2n. The accumulator 320 keeps adding 2n from the step sizer 340 in succession to provide repeatedly accumulated 2n values (2xc3x972n, 3xc3x972n, 4xc3x972n, 5xc3x972n, 6xc3x972n, - - - , 22nxe2x88x922n) as addresses of a first column of the transposing memory 102. Then, the second counter 330, which provides a number of repetitions generates a carry out, and the first counter 300 is enabled by the carry out to provide xe2x80x981xe2x80x99, and the initial value generator 310 initializes the accumulator 320 at xe2x80x981xe2x80x99. Accordingly, the accumulator 320 provides xe2x80x981xe2x80x99, and then the 2n from the step sizer 340 is repeatedly added to the xe2x80x981xe2x80x99 from the accumulator 320 for 2n times to provide addresses of the second column (xe2x80x981xe2x80x99,1+2n, 1+2xc3x972n, 1+3xc3x972n, 1+4xc3x972n, 1+5xc3x972n, 1+6xc3x972n, - - - , 1+22nxe2x88x922n). In the same manner, the first counter 300 provides 2, 3, 4, 5, 6, and 7, and the accumulator repeatedly accumulates the 2n from the step sizer 340 for 2n times whenever the first counter 300 provides the 2, 3, 4, 5, 6, and 7. Thus, the column direction address generator can generate column direction reading addresses for all columns of the 2nxc3x972n transposing memory.
As described above, however, the related art encoder has various problems in the column direction address generator. First, the two counters and two accumulators in the related art column direction address generator make the hardware complicated, which is difficult (e.g., increased size, increased cost, increased time, etc.) to fabricate. Further, initialization of each of the counters, the initial value generator, and the accumulator at an appropriate time required for generation of the column direction address generator makes an encoding or decoding rate of the picture data decrease or slow.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
An object of the present invention is to provide a device that generates memory addresses, a mobile station by using the same, and a method for writing/reading a data that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
Another object of the present invention is to provide a device for generating memory addresses that has reduced size.
Another object of the present invention is to provide a device for generating memory addresses that has reduced cost.
Another object of the present invention is to provide a device for generating memory addresses, which can generate column direction addresses of a transposing memory faster and more efficiently.
Another object of the present invention is to provide a device for generating memory addresses and a method for writing/reading a data, in which column direction addresses and row direction addresses of a transposing memory can be processed in parallel to generate the column direction address and the row direction address on the same time, alternatively.
To achieve at least these objects and other advantages in a whole or in part and in accordance with the purpose of the present invention, as embodied and broadly described, a memory address generator includes a counter that generates 22n addresses in 2n bitstreams in succession to provide row direction addresses, and a barrel shifter that subjects the generated 2n bitstreams to xe2x80x98nxe2x80x99 bit barrel shifting to provide column direction addresses.
To further achieve the above objects in a whole or in part in accordance with the present invention, there is provided a memory address generator including a counter that generates 22n addresses in succession to provide a first 2n bitstream and a second 2n bitstream having the first 2n bitstream shifted by xe2x80x98nxe2x80x99 bits, and a multiplexer that selects one from the first 2n bitstream and the second 2n bitstream in response to a selection signal.
To further achieve the above objects in a whole or in part in accordance with the present invention, there is provided a memory address generator that includes a counter that generates a plurality of addresses with a prescribed number of bits in succession to provide first direction addresses and a shifter that shifts the successive prescribed bit addresses by xe2x80x98nxe2x80x99 bits to provide second direction addresses.
To further achieve the above objects in a whole or in part in accordance with the present invention, there is provided a mobile station for encoding and transmitting a picture data that includes a transposing memory that stores the picture data, a memory writing address generator that alternatively generates writing addresses of the transposing memory in a row direction and in a column direction in response to a first control signal, and a memory reading address generator that alternatively generates reading addresses of the transposing memory in the column direction and in the row direction in response to a second control signal.
To further achieve the above objects in a whole or in part in accordance with the present invention, there is provided a method for transferring data for a transposing memory having a prescribed number of cells that includes storing a first periodic prescribed number of data in a row direction in the transposing memory in succession, reading the first periodic data in a column direction in succession beginning when a preset number of the first periodic data are stored in the row direction, storing a second periodic prescribed number of data in the transposing memory in the column direction in succession, and reading the second periodic data in the row direction in succession.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.